A low temperature poly-silicon thin film transistor (LTPS-TFT) display has advantages such as high resolution, quick response, high brightness, high aperture ratio, and so on. LTPS has high electron mobility due to its characteristics. In addition, peripheral driving circuits can be prepared on a glass substrate at the same time, realizing system integration, saving space and costs for driving ICs, and reducing the product defect rate.
Currently, the method for manufacturing a low temperature poly-silicon thin film field effect transistor includes the following steps:
S101, as shown in FIG. 1, forming a poly-silicon layer 20 on a base substrate 10. The poly-silicon layer 20 includes a first poly-silicon area 201, second poly-silicon areas located at the both sides of the first poly-silicon area 201, and third poly-silicon areas 203 located at a side of each second poly-silicon area 202 away from the first poly-silicon area 201.
S102, as shown in FIG. 2, subsequently forming a gate insulation layer 30, a gate metal film and a photoresist film on the base substrate on which the poly-silicon layer 20 has been formed, exposing and developing the photoresist film to obtain a photoresist fully retained portion 401, a photoresist half retained portion 402 and a photoresist fully removed portion. The photoresist fully retained portion 401 corresponds to the first poly-silicon area 201, the photoresist half retained portion 402 corresponds to the second poly-silicon areas 202, and the photoresist fully removed portion corresponds to the rest areas. The gate metal film on the photoresist fully removed portion is removed by a wet etching method, so as to obtain the gate metal film 50a corresponding to the photoresist fully retained portion 401 and the photoresist half retained portion 402.
S103, as shown in FIG. 3, with the photoresist fully retained portion 401 and the photoresist half retained portion 402 as a mask, performing N+ doping into the exposed third poly-silicon areas 203 to form heavily doped areas 203a. 
S104, as shown in FIG. 4, removing the photoresist in the photoresist half retained portion 402 by an ashing process, and performing wet etching with respect to the exposed gate metal film to form a gate electrode 50.
S105, as shown in FIG. 5, with the gate electrode 50 as a mask, performing light doping into the exposed second poly-silicon areas 202 to form lightly doped areas 202a. In the case shown in FIG. 5, the first poly-silicon area 201, the lightly doped areas 202a, the heavily doped areas 203a construct an active layer 20a. 
S106, as shown in FIG. 6, forming a protection layer 60 as well as a source electrode 701, a drain electrode 702, etc. on the base substrate on which the above steps have been completed.